Traditionally, the dynamic random access memory (DRAM) chips used in a personal computer system are manufactured using a different semiconductor process technology than the semiconductor process technology used to manufacturer the processor for the personal computer system. The process technology for creating large high-density memory circuits required additional steps not used in a traditional CMOS process for creating digital semiconductor devices. Thus, in most personal computer systems, the processor is implemented on one chip and the main memory is implemented on other chips. The personal computer system is constructed by coupling together the processor chip, the DRAM chips, and a few other support chips on a printed circuit board.
The main memory technology available within CMOS digital circuits has been static random access memory (SRAM). SRAM technology provides very good performance but SRAM has a low bit density (amount of bits per unit of area) and consumes a relatively large amount of power. However, in recent years, embedded dynamic random access memory (eDRAM) circuitry that is constructed using the industry standard CMOS fabrication processes has become available. Embedded DRAM (eDRAM) has become a popular technology for use within Application Specific Integrated Circuits (ASICs) since eDRAM allows an entire computer system (both the processor and the main memory) to be implemented within a single integrated circuit.
eDRAM (and traditional DRAM) is constructed as an array of individual memory cells. Each memory cell uses a capacitor to stores an electrical charge value that represents a data bit. However, since capacitors leak electrical charge over time, the charge on the capacitor must be periodically refreshed or else the memory cell will lose the stored data value. Thus, every DRAM device requires memory refresh circuitry that periodically scans through the array of memory cells and refreshes the electrical charge stored on the capacitor within every memory cell. When a memory cell is being refreshed, that particular memory cell cannot be accessed by other circuitry for reading and writing to the memory cell. Thus, memory refresh circuitry uses valuable memory bandwidth. Therefore, it is desirable to have memory refresh circuitry that efficiently refreshes memory cells without unnecessarily using up too many resources such as available memory cycles.